Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 1 Beispiel Cache-Architektur
Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 2 Number entries in cache ≙ number cache lines = Cache size / block size 32 * 1024 Byte / 4 Byte = 2 5 * 2 10 / 2 2 = 2 13 cache lines → 13 Bits are necessary for cache line address Given Cache Size: 32 KByte block size: 4 Byte Organization form: direct mapping DatenTag 0x x1FFF...
Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 3 Speicher Size: 1 MByte ≙ 2 20 Byte Access to memory under address 0x103450b → 0x00000 Memory... 0x xFFFFF... 0x12 0x42 0x18 0x50
Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 4 0x00D1 Which cache line, which tag? 4 = 2 2 Byte size of block 2 13 cache lines 0x b TagCache line 0b Byte-Nr 0x00000 Memory... 0x xFFFFF... DatenTag 0x x1FFF... 0x x x x00D x x12 0x42 0x18 0x50 0x12 0x42 0x18 0x50 {
Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 5 Number of entries in cache ≙ number of cache lines = cache size / block size / degree of associativity (32 * 1024 Byte / 4 Byte) / 2 = 2 5 * 2 10 / 2 3 = 2 12 cache sets → 12 Bits are necessary for cache line address Given Cache Size: 32 KByte block size: 4 Byte Organization form: now 2-way associative DatenTag 0x xFFF... 0x001...
Lehrstuhl für Informatik 3 - D. Fey Vorlesung GRa - SS , Folie 6 0x0D1 Which cache line, which tag? 4 = 2 2 Byte block size 2 12 cache lines 0x b TagCache-Menge 0b Byte-Nr 0x00000 Memory... 0x xFFFFF... DatenTag 0x xFFF... 0x x x x0D x x12 0x42 0x18 0x50 0x12 0x42 0x50 { 0x120x420x180x50 0x120x420x180x50 0x Can be stored in both lines