Www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology.

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1 www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology Karlsruhe Institute of Technology (KIT) CONDOR Plenary Eningen 28-29.07.2011

2 Condor Übersicht (DSP) Basisstationen senden Auf eigenen Frequenzbändern Basisstationen empfangen Mischprodukt aller benachbarten Basisstationen -------------------------------------------------- DSP Stufe 1: Auftrennung Heruntermischen und Filtern der Teilspektren (parallel) Downsampling (parallel) -------------------------------------------------------------- DSP Stufe 2: Verarbeitung (parallel) Flexibler System on Chip Ansatz Getrenntes prozessieren der Spektren ermöglicht getrennte Korrektur von Störungen (LO-Offsets, Laufzeit, etc.) 4 Gb/s pro Empfänger geplant © Institute for Information Processing Technology - 11 Mai, 2011 KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 2 |

3 Filter stage KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 3 | © Institute for Information Processing Technology - 11 Mai, 2011 High-Speed FIR Filter zur Selektion der gewünschten Subcarrier Konventionelles FIR Filter benötigt auf FPGA nicht realisierbare Taktfrequenz Lösung: Parallelisierung des klassischen FIR-Filters Möglicher Frequenzgang des Selektionsfilters

4 Beispielfilter KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 4 | © Institute for Information Processing Technology - 11 Mai, 2011 Raised-Cosinus Filter mit 48 Taps Abtastfrequenz F S = 25GHz Knickfrequenz F C = 1GHz

5 OFDM Signalverarbeitung KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 5 | © Institute for Information Processing Technology - 11 Mai, 2011 System on Chip Konzept AHB SOC Bussystem mit AHB Matrix in Kombination mit On-Chip Speicher-Ressourcen für genügend Speicherbandbreite Multiprozessorsystem aus Application Specific Instruction Set Prozessoren (ASIP) Flexibilität in Performanz durch einfache Anpassungsmöglichkeiten der Hardware (Prozessoranzahl nur durch FPGA beschränkt) Flexibilität der Anwendung durch Programmierbarkeit der Prozessoren Verhältnismäßig einfache ASIC Anpassung (Takt vs. ASIP Anzahl)

6 SOC – Tx more detailed overview KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 6 | © Institute for Information Processing Technology - 11 Mai, 2011

7 SOC – Tx Signal Processing System KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 7 | © Institute for Information Processing Technology - 11 Mai, 2011 Signal Processing System (SPS – Blue) Subsystem to perform the OFDM signal processing 64 bit AHB Multilayer System Mainly build of OFDM-specific ASIPs and a high amount of Block RAM All IP Cores are custom developments

8 SOC – Tx Control system KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 8 | © Institute for Information Processing Technology - 11 Mai, 2011 Control System (CS – green) Subsystem to configure, manage and control the SPS 32 bit AHB/APB System Leon3 processor (SPARC-V8 Architecture) Mainly build from Aeroflex-Gaisler IP-cores (GPL)

9 SOC – Tx Status KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 9 | © Institute for Information Processing Technology - 11 Mai, 2011

10 AHB Multilayer Matrix Multilayer Enables multiple parallel transfers Supports standard AHB components Interconnect Matrix Controls switching of bus signals to build connections between Masters and Slaves Implements arbitration Performance scalability of SPS depends heavily on the Scalability of the AHB matrix! KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 10 | © Institute for Information Processing Technology - 11 Mai, 2011

11 AHB Matrix - resources First working version (Post Synthesis results with xst) 2 nd Implementation with delayed arbitration (3 clock cycles) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 11 | © Institute for Information Processing Technology - 11 Mai, 2011 Matrix Form (MxS)RegisterLUTMax clk 4x4 825 1 456107.552MHz 4x321 025 8 410104.176 MHz 16x323 93941 34126.651MHz Matrix Form (MxS)RegisterLUTMax clk 4x4 767 1 421344.931MHz 4x321 0101 969254.904MHz 16x324 75614 442229.948MHz

12 Unidirectional AHB 2 AHB Bridge Exchange of data … …between control system (CS) Standard AHB 32-bit wide ~100-150 MHz … signal processing system (SPS) Multilayer AHB 64-bit wide ~200 MHz Implementation APB controlled FSM writes/reads any data to/from SPS to a Block RAM Short access times due to usage of the full bus performance (64bit, 200MHz) instead of mapping every single transfer Block RAM can be written/read from CS as well KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 12 | © Institute for Information Processing Technology - 11 Mai, 2011 RegisterLUTBRAMMax clk 248 320 2476 MHz

13 FFT – ASIP FFT Processor Radix 2 Module, Twiddle factor multiplication, Twiddle Factor Generation, Address Generator, AHB Master Interface, programmable Control FSM Pipelined Radix 2 Butterfly: 3 clocks per Operation 4 stages with one butterfly each:  natural ASIP FFT-size :16-point Bigger FFT-sizes are build by break them down into several 16-points FFTs + reordering Example on the right side 4-point FFT ASIPs 2 Butterflys, 2 Stages 16-point FFT by 8 4-point FFTs and corresponding reordering KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 13 | © Institute for Information Processing Technology - 11 Mai, 2011

14 Demonstrator numbers Example Samplerate : 1GS/s CS: 100 MHz clock frequency, 32 bit wide AHB SPS: 200 MHz clock frequency, 64 bit wide multilayer AHB 16 bits resolution  32 bit per OFDM Symbol FFT size: 256 (8 stages  2 ASIPs concatenated) Cyclic Prefix size: worst case ¼ Performance: 1GS/s, QAM16 : ~3Gb/s (cyclic prefix, pilottones!) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 14 | © Institute for Information Processing Technology - 11 Mai, 2011

15 Demonstrator Hardware KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 15 | © Institute for Information Processing Technology - 11 Mai, 2011

16 Vielen Dank für ihre Aufmerksamkeit Fragen? KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 16 | © Institute for Information Processing Technology - 11 Mai, 2011