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H.-G. Moser July 25, 2012 PXD Summary Agenda: PXD Session: July 23, 2012 This talk: selected topics (excuses, don’t feel neglected!) 1 17:00Introduction.

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Präsentation zum Thema: "H.-G. Moser July 25, 2012 PXD Summary Agenda: PXD Session: July 23, 2012 This talk: selected topics (excuses, don’t feel neglected!) 1 17:00Introduction."—  Präsentation transkript:

1 H.-G. Moser July 25, 2012 PXD Summary Agenda: PXD Session: July 23, 2012 This talk: selected topics (excuses, don’t feel neglected!) 1 17:00Introduction (15')Christian Kiesling 17:15DEPFET Status (30')Rainer Richter 17:45EMCM, 3rd metal, flip-chip (15')Laci Andricek 18:00Lab Tests, Irradiations (20')Jelena Ninkovic 18:20Test Beam Results (15')Carlos Marinas 18:35Electronics (ASICs, DHH, DCE) (30') Ivan Peric 19:05Services, Power (20')Stefan Rummel 19:25Cooling/Mockups (15')Carsten Niebuhr 19:40Summary of PXD/TRG workshop at Bayrischzell (10') Allen Campbell

2 H.-G. Moser July 25, 2012 Highlights 2 SOI wafers PXD9 production start Gated Mode Irradiations ASIC,Testbeam, EMCM, DAQ Milestones

3 H.-G. Moser July 25, 2012 Thin Sensors -> SOI Material 3 Wafer bonding SOI process Thinning of top wafer (CMP) Processing etching of handle wafer (structured) 450  m 50  m Cut through the matrix Many steps performed by industry Result must comply with our qualtiy requirements

4 H.-G. Moser July 25, 2012 SOI: ICEMOS 4 February 2012: ICEMOS SOI wafers had rough surfaces in the terrace area which caused unacceptable particle contamination Had to stop sensor production New wafers arrived in May Thinned and polished by Rockwood Quality ok Diode production showed acceptable currents Start PXD9 with 13 wafers Ordered additional 40 SOI wafer from ICMOS for 2 nd PXD9 batch

5 H.-G. Moser July 25, 2012 SOI: Shin Etsu 5 Shin Etsu agreed to produce 5 test wafers First two wafers show good quality: Very good polishing Extremly low metal contaminations However some roughness of the top wafer edge and (very few) etch pits were found Recently we got the remaining wafers, Shin Etsu ‘fine tuned’ their process Quality improved and is now very good We gave Shin Etsu green light to produce 30 SOI wafers Thanks to Laci Andricek who worked on the SOI for years!

6 H.-G. Moser July 25, 2012 PXD9 Production Inner outer 6 Wafer bonding SOI process Thinning of top wafer (CMP) Processing etching of handle wafer (structured)

7 H.-G. Moser July 25, 2012 PXD9 Production Inner outer 7 RR: 1Feuchte Oxidation, fox2-950, 90nm, davor DCE-clean, evtl. trocken in MPI1-409.07.2012 2Litho ALIP neu, justiert auf vergra. ALIB, MA-IR, p-Seite16.07.2012 3Litho ALIN neu + DWL-Wafernummern, MA-VR auf ALIP23.07.2012 4Th. Oxid durchätzen, beidseitigx 52. Implantation ND0N, P 500 keV, 1E11 cm-2, n-Seite, unmaskiertx 6LPCVD-Nitrid1, 20 nmx 7LPCVD-Poly1, 550°C, 600 nmx 8LPCVD-LTO1, 105nmx 93. Implantation Poly1, n-Seite, P 140keV, 8E15cm-2x 10Rekristallisation, EANN-900, 1hx 112. Lithographie PO1N, justiert auf ALINx 12Strukturierung LTO1 n-Seite, SEZx 13Strukturierung Poly1 n-Seite, SEZ, defreckle (30% + 30sek defreckle)x 14LTO1 beidseitig abätzen, SEZx 153. Lithographie PSHNx 164. P-Kanal Implantation, 30keV, 1.5E12, Dualmodex 174. Lithographie PDPNx 185. Deep P-Implantation, B 210 keV, 1.5E12 cm-2x 19Oxidation Poly1, FOX2-900, 215nmx 20Oxinitridschicht entfernen, 2 min HF-Dipx 21Nitrid1 durchätzen, n-Seitex 227. Lithographie NOXNx 238. N+ Implantation, As 180keV, 7E14, Quadmode, Strombegrenzung (300µA)!x 245. Lithographie ND1Nx 256. Deep N-Implantation, P 500 keV, 8E11 cm-2, Dualmode?x 26LPCVD-Nitrid2, 730°C, 30nmx 27LPCVD-Poly2, 550°C, 500nmx 28LPCVD-LTO2, 105nmx 299. Implantation Poly2, n-Seite, P 140keV, 8E15cm-2x 30Rekristallisation, EANN-900, 1hx 318. Lithographie PO2Nx 32Strukturierung LTO2 n-Seite, SEZx 33Strukturierung Poly2 n-Seite, SEZ, defreckle (30% + 30sek defreckle)x 34LTO2 beidseitig abätzen, SEZx 35Poly2, p-Seite abätzen, SEZx 36Poly2 FOX2-900, 215nm?, evtl. wird die POXN vorgezogen! Rarx 37Nitrid2 durchätzen, beidseitig, davor 2min HF-Dipx 389. Lithographie POXNx 398. P+ Implantation, B 25keV, 1E15cm-2, Quadmode!!x 40Polyoxid1 p-Seite abätzen, SEZx 41Poly1 p-Seite abätzen, SEZx 42defreckle p-Seitex 43LPCVD-Nitrid3, d=30nmx 44LPCVD-LTO3, d=300nmx 45LTO3 abätzen ganzflächig, p-Seite, SEZx 4610. Lithographie NITNx 47LTO3 strukturieren, n-Seite, SAT1x 48Nitrid beidseitig durchätzen, n-Seite Nitrid3, p-Seite Nitrid1+3 -> th. Ox liegt freix 49NITDANN+H2T-450x 5011. Lithographie CO1Nx 51Oxide öffnen, n-Seitex 52Metallisierung hot alu, n-Seitex 5312. Lithographie AL1Nx 54Hotalu strukturieren n-Seitex 5513. Litho FRECN (invertierte und vergrößerte KO1N)x 56Defreckle-etch, n-Seitex 57El. Messenx 5814. Lithographie AOXNx 59Aluoxidation HOT-DIx 60LPCVD-LTO4 600/1000nm?x 6115. Lithographie KO2N, justiert auf al1nx 62LTO4 strukturieren, n-Seite, SAT2-padetchx 63Metallisierung cold alu, n-Seite, softetch!x 6416. Lithographie AL2Nx 65Alu2 strukturieren n-Seitex 66El. Messen 6717. Lithographie WINP, p-Seite, justiert auf ALIPx 68600-1000nm LTO4 + 85nm th. Oxid durchätzen, p-Seitex 69H2T-400x 70BCBNx 71BCBP, als Schutz für die TMAH-Ätzungx Entwicklungslabor:x 72Waferholder n-Seite, TMAH-Ätzung p-Seitex 738. Lithographie KONP, p-Seite, MA Justage auf ALIPx 74Therm. Oxid p-Seite durchätzenx 75Sputtervorreinigung: Schutzlack n-Seite, HF-Dip 60 sek, LM-Reinigungx RR: 76Metallisierung cold alu, p-Seitex Entwicklungslabor:x 7712. Lithographie ALUP, MA justiert auf ALIPx 78Alu strukturieren p-Seitex 79H2T-320, davor + danach el. Messenx 80Endreinigung, Endkontrollex 81bcbn/bcbp?x 92cutn/cutpx 92 steps/25 Masks Many improvements in design and technology to improve yield but keep performance of PXD6 E.g. Al 2 O 3 protection layer to reduce hillocks (Al – Al shorts) Increase internal spacing to provide more room for contact lines

8 H.-G. Moser July 25, 2012 Production Schedule 8 Total production time of a batch: 2 years First wafers leave clean room (before thinning): End 2013: yield test! First sensors available (thinned and cut): July 2014

9 H.-G. Moser July 25, 2012 Injection Noise & Gating 9 Normal operation: Signal charge drifts into internal gate Gated Mode Charges from background drift directly to clear gate Signal already stored in internal gate is protected

10 H.-G. Moser July 25, 2012 Gated Mode: Measurements 10 Gated mode successfully tested in the lab (laser) and test beam TB: Signal distribution of pixels which have been hit by a track when gated was on (from track extrapolation) MC: normal noise distribution A real signal should be here Protection: the signal of a real hit is still present after gating: Signal before gate (not cleared) Signal after gate Gate on

11 H.-G. Moser July 25, 2012 Gated Mode: System Aspects 11 Problem: the clear gates of all pixels have to be pulsed within 1µs => Large capacitance (16nF), large peak currents, instable control signals Decoupling 10nF Decoupling 100nF More simulations needed Have to optimize circuit and place additional decoupling capacitors (where?) Switcher modified for gating has already been submitted (back in September) Exact timing and synchronization still needs to be fixed Gating w/ or w/o readout?

12 H.-G. Moser July 25, 2012 Radiation Hardness 12 PXD6 matrix was irradiated with 10MeV electrons and tested with a Strontium source  Matrix works fine after irradiations (15kG)  Threshold voltage shift ~0.5V higher than after  irradiation Threshold voltage shift of 10V after 100kG (10Mrad) for clear gates is a bit on the high side  parameter for PXD9 changed to reduce effect  3-times segmentation to fine tune along matrix (but: background seems to be uniform anyway) Low energy electrons from background cause bulk damage. => increase leakage currents  however, measured damage factor only 1% instead of 6% compared to 1 MeV neutrons!  Expected effect very small: additional 19e noise

13 H.-G. Moser July 25, 2012 AOB 13 ASICs: Have prototypes of all ASICs Switcher18: resubmitted with mods. for gating DHP: to be re-designed for TSMC 65nm (test chip works, irradiation tested (damage and SEU): ok Test Beam: nice, new results Efficiency > 99.5% 3 rd metal copper: Nice progress Flip chip tests started EMCM: 50% produced, Ready in September DCD Switcher DHPDCE

14 H.-G. Moser July 25, 2012 PXD/DAQ/TRG workshop Bayrischzell, July 22-25 14 Many points to discuss, e.g.timing of trigger signals

15 H.-G. Moser July 25, 2012 Milestones 15 done next

16 H.-G. Moser July 25, 2012 Conclusions Good news: SOI problems resolved (ICEMOS & Shin Etsu). PXD9 production has started Injection Noise: Gated operation demonstrated in test beam Working on system implementation Modified switcher submitted Background occupancy and radiation damage under control We have working prototypes of all ASICs (Milestone!) Not covered in this talk: Good progress for: DHH/DAQ, Power Supplies, Services, Cooling … 16

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