CSL211 Computer Architecture

Präsentation zum Thema: "CSL211 Computer Architecture"—  Präsentation transkript:

1 CSL211 Computer Architecture
Processor design - Introduction 30th August, 2011

2 MIPS subset for implementation
Arithmetic - logic instructions add, sub, and, or, slt Memory reference instructions lw, sw Control flow instructions beq, j Incremental changes in the design to include other instructions will be discussed later

3 Format of instructions
lw, sw, beq I - format op rs rt 16 bit number j J - format op bit number add, sub, and, or, slt R - format op rs rt rd shamt funct

4 Generic Implementation
use the program counter (PC) to supply instruction address get the instruction from memory read registers use the instruction to decide exactly what to do

5 Design overview R e g i s t r # D a m o y A d P C I n u c L U

6 Division into data path and control
signals status signals CONTROLLER

7 Building block types Two types of functional units:
elements that operate on data values (combinational) output is function of current input no memory elements that contain state (sequential) output is function of current and previous inputs state = memory

8 Combinational circuit examples
gates: and, or, nand, nor, xor, inverter multiplexer decoder adder, subtractor, comparator ALU array multipliers

9 Sequential circuit examples
flip-flops counters registers register files memories

10 Clocked vs. unclocked circuit
Clocked state element state changes only with clock edge Unclocked state element state changes can occur with changes in other inputs cycle time rising edge falling edge

11 Unclocked state elements
Q _ R S D C Q

12 Clocked state elements
Q _ D l a t c h C D C Q

13 Clock and timings S t a e l m n 1 C o b i g c 2 C l o c k y e

14 Components for MIPS subset
Register Adder ALU Multiplexer Register file Program memory Data memory Bit manipulation components

15 MIPS components - register
PC clock 32

16 MIPS components - adder
32 PC 4 + 32 PC+4 offset +

17 MIPS components - ALU 32 operation result a b ALU a=b overflow

18 MIPS components - multiplexers
mux 1 32 PC+4 PC+4+offset select

19 MIPS components - register file
W r i t s a d 1 2 D n u m b 5

20 MIPS components - program memory
u c i o m e y a d

21 MIPS components - data memory
W r i t D o y A s

22 MIPS components - bit manipulation circuits
sign xtend MSB 16 32 LSB shift MSB 32 32 LSB

23 Datapath for add,sub,and,or,slt
fetch instruction address the register file pass operands to ALU actions pass result to register file required increment PC Format: add $t0, $s1, $s2 op rs rt rd shamt funct

24 Fetching instruction IM ad ins PC

25 Addressing RF IM RF ins[25-21] rad1 ins[20-16] rd1 PC ad rad2 ins rd2
wad wd rd1 rd2 PC ad ins

26 Passing operands to ALU
ins[25-21] ins[20-16] IM rad1 RF rd1 ALU PC ad rad2 ins rd2 wad wd

27 Passing the result to RF
ins[25-21] IM rad1 RF ad ins[20-16] rd1 PC rad2 ins ALU rd2 wad ins[15-11] wd

28 Incrementing PC + IM ALU 4 RF ins[25-21] rad1 ins[20-16] rd1 PC ad
wad ins[15-11] wd

29 Load and Store instructions
format : I Example: lw $t0, 32($s2) op rs rt bit number

30 Adding “sw” instruction
+ 4 ins[25-21] IM rad1 RF ins[20-16] rd1 PC ad rad2 ALU DM ad rd wd ins rd2 wad 1 ins[15-11] sx ins[15-0] 16 wd

31 Adding “lw” instruction
+ 4 ins[25-21] IM rad1 RF ins[20-16] rd1 PC ad rad2 ins ALU DM 1 rd2 wad 1 ad rd 1 ins[15-11] wd wd 16 sx ins[15-0]

32 Format of beq instruction
beq I - format op rs rt 16 bit number

33 Adding “beq” instruction
+ s2 1 + 4 ins[25-21] IM rad1 RF ins[20-16] rd1 PC ad rad2 ins ALU DM 1 rd2 wad 1 ad rd 1 ins[15-11] wd wd 16 sx ins[15-0]

34 MIPS components - bit manipulation circuits
sign xtend MSB 16 32 LSB shift MSB 32 32 LSB

35 Format of jump instruction
j J - format op bit number

36 Adding “j” instruction
1 s2 ins[25-0] PC+4[31-28] ja[31-0] 28 1 + + 4 s2 ins[25-21] IM rad1 RF ins[20-16] rd1 PC ad rad2 ins ALU DM 1 rd2 wad 1 ad rd 1 ins[15-11] wd wd 16 sx ins[15-0]

37 Control signals s2 + + s2 IM ALU sx 4 RF DM jmp ins[25-0] 28 ja[31-0]
ja[31-0] 1 PC+4[31-28] + + Psrc 4 s2 RW ins[25-21] IM rad1 RF Z MW M2R ins[20-16] rd1 PC ad rad2 Asrc DM ins ALU 1 rd2 wad 1 ad rd 1 ins[15-11] wd op 3 Rdst wd 16 sx MR ins[15-0]

38 Datapath + Control s2 + + s2 control IM ALU sx Actrl 4 RF DM jmp
ins[25-0] 28 s2 1 ja[31-0] 1 PC+4[31-28] + + brn Psrc 4 s2 control ins[31-26] opc 2 RW ins[25-21] IM rad1 RF Z MW rd1 PC ad ins[20-16] M2R rad2 ALU DM ins Asrc 1 rd2 wad 1 ad rd 1 ins[15-11] wd op Actrl ins[5-0] 3 wd Rdst 16 sx ins[15-0] MR

39 Summary Processor designed for {add, sub, and, or, slt, lw, sw, beq, j} Step by step approach Started with {add, sub, and, or, slt} Added {sw, lw}, then added {beq, j} Identified control signals and connected to a controller (black box).