Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 1 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Part 4 Fundamentals in Computer Technology Computer Architecture Slide Sets WS 2010/2011 Prof. Dr. Uwe Brinkschulte Prof. Dr. Klaus Waldschmidt

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 2 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Technology trends: things are getting smarter

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 3 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Technology trends: networked systems of the future Networked Systems pervasive computing disappearing computer ambient intelligence ubiquitous computing

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 4 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Technology trends: heterogeneous hardware-software-systems (HW/SW) System on Chip Processor-Core, FPGA, RF, Bluetooth... + Software Heterogeneity also in the environment (application)

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 5 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Technology trends: cyber physical systems (CPS) Integration of physical systems and networked computing In classical embedded systems, the physical environment is controlled by the computer In cyber physical systems, the physical environement and the computer(s) closely interact and cooperate Examples: power grids, networks of autonomoues vehicles, air traffic control, …

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 6 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt System-on-Chip System on Chip (SoC) Functional and technology aspects Technology Aspects: Process Combinations necessary Analog/Digital Systems: Components, Interfaces + Technologies

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 7 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A AD/DA D An analog component with a digital processor core Embedded digital processors are mainly used in analog environments. Life science and technical applications are mainly analog. Therefore, an analog to digital conversion and vice versa is necessary.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 8 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Microprocessor Important component of all modern analog and digital applications. It became the basic measure for the technological progress in VLSI. It became the workhorse of all modern IT applications

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 9 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Modern processor chips Intel Pentium Processor System-on-Chip (Bluetooth SoC: Eynde et al., Alcatel, 2001) Analog Devices ADSP Intel Pentium IV IBM Power PC 750 Microphotographs of processor chip layout Altera FPGA with ARM-core

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 10 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt P III 1M 10M 100K 10K Pentium M 1000 M P IV CMOS until to the end of the Moore era (end of this decade) The Moore curve # transistors This prediction of Gordon Moore demonstrates the progress of technology in the last decades. The complexity of integrated circuits (VLSI) doubles every 18 month. year Silicon will be the basic material for the next years.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 11 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt The scaling (c) ,05 0,1 0,15 0,2 year 20000, , , , , , , , ,01 Strukture size [µm] The area scales with c 2 Signal delay of active components scales with c Signal delay of passive components will be nearly constant Signal delays are dominated by the delay of the wires (passive components) wire-centered design instead of only logic optimized design or better a combination of both Structure size [µm] c year

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 12 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Architecture Level Microarchitecture Level Register Transfer Level Gate Level Transistore Level Charge Level …

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 13 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Computer Architecture Level Instruction Set Architecture, Memory Sizes, Clock Frequency, …

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 14 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Computer Microprocessor, CPU control unit functional unit (datapath) memory (program, data) input/output connection (bus) Microarchitecture Level

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 15 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Register Transfer Level state register next state output function control unit instruction (program) data register functional units data in data path data path control CPU

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 16 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt functional unit A top down look at computer technology Gate Level & & 1 1 e 1 e 2 e 3 a

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 17 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Transistor Level

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 18 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A top down look at computer technology Charge Level

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 19 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Planar process technology Passivation (field oxide) oxide 4 oxide 3 oxide 2 oxide 1 substrate metal layer 3 metal layer 2 metal layer 1 Polysilicon transistor capacitance metal to substrate capacitance metal to metal oxide = SiO 2 Delay times

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 20 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Modeling of signal delays in wires for the connection of active components (gates) in chip-layouts Voltage at node n j for a given input voltage U E Delay t d at node n: Solution: Approximative solution of the differential equation for R i = R 0 Vi C i = C 0 Vi per 1 µm of wire length current through the capacitance at node j RnRn R1R1 R2R2 UEUE C1C1 C2C2 CnCn unun Differential Equation: Wire: Model: 1µm Total resistance at node j Delay times

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 21 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Typical values for resistance, capacitance and the resulting delay times for integrated wires t dD 6,3R D 7C JN 1,8n-diffusion t dP 1,3R P 17C PF 0,15polysilicon t dm 0,001R M 0,02C MF 0,1metal delay time ns per 1mm 3µm resistance /µm capacitance fF/µm

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 22 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt 300 Ω 300 Ω 300 Ω R 1 R 2 R 3 measure point 1measure point 2measure point 3measure point 4 UEUE C1 C2 C3 350fF 350 fF 350 fF Example of a real wire model

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 23 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Plot of the node voltage at different measure points per wire length measure point 1 measure point 2 measure point 3 measure point 4 measure point 3 measure point 2 measure point 1 4,0 V 2,0 V 0 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 24 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt The clock Example: - 10 GHz clock frequency (0,1 ns clock period) - 30 mm distance between two components means 10 clock cycles on the wire (silicon) The clock skew in this example is 1 ns. It is too high for sequential synchronous circuits. The clock skew has to be considered in the design phase and /or has to be avoided by architectural solutions. (clock tree, wave pipelining, etc.) The increasing size of modern chips (chip area) means, that also the connections between the components on the chip become longer.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 25 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Memory gap wire capacity memory capacity memory transistor Typical design of a DRAM cell Access time is dominated by charging and decharching of the memory capacity: t a = R transistor C memory capacity C is limited above 10 fF to avoid data loss by alpha particles R is limited by the area of the memory transistor => t a is limited

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 26 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Memory gap The memory capacity scales to the square with the size of the chip As seen before, access time does unfortunately not scale this way Therefore a memory gap exists. Increasing clock speed generates an increasing memory gap. Caches are a good solution but they can bridge the gap only unsufficient because of the limited locality of typical programs. Because of the memory gap, an increasing clock speed results not automatically in a higher execution- speed of programs. memory gap

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 27 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Unbalanced von Neumann CPU caches,... vN bottleneck

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 28 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Reduction of power and energy consumption is a big issue today On high end systems, heat dissipation has to be reduced Modern mobile embedded systems need the reduction to increase battery lifetime => Tradeoff between high performance and low power/energy consumption Main ways to reduce power and energy consumption Reduction of clock frequency Reduction of supply voltage Optimization of microarchitecture Power consumption

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 29 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Power consumption and clock frequency As seen before, CMOS only consumes power when switching Therefore, in modern gate technologies the energy consumption is mostly proportional to the clock frequency P ~ f Reduction of clock frequence means reduction of power consumption, but as well a reduction of the system performance

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 30 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt The power supply voltage The power supply voltage cannot easily be reduced under 1-0,5 V voltage High Performance [V] voltage Low Power [V] 0,5 1,0 1,5 year 19991,81, ,81, ,51, ,51, ,51, ,20, ,20, ,90, ,60, ,60,3 Voltage High Performance [V] Voltage Low Power [V] year The reduction of supply voltage implies a reduction of max. clock frequency. P ~ U 2

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 31 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Possible approaches: Reduction of external bus activities (stay local) Static Power Management (sleep instructions) Dynamic Power Management (control unit deactivates non-used parts of the microarchitecture) Increase of code density (saves memory space and cycles) Power consumption and microarchitecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 32 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Example: reducing memory power consumption This disadvantage of a good memory hierarchy is a high degree in energy consumption. The on-chip data - and instruction caches need itself appr. 25 % of the total power of a processor chip. CPU kernel instructions other instructions Instruction Cache Kernel Memory (small and fast) Off-Chip memory common address space A cache oriented solution as an example for a power aware microarchitecture.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 33 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt SIA-Roadmap , , , year chip area [mm²] transistors/ chip [Mio] year frequency [Mhz] power con- sumption [W] chip area [mm²] transistors/chip [Mio] frequency [MHz] power consumption [W] year

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 34 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt The challenge (limit) of chip technology in the future The production of chips with layout structures in dimensions under 0.1 µm became very difficult with respect to lithography. Therefore, only about 10% of todays chips are produced using latest technology Chips of more than 300 mm 2 chip area will include one or more faults in average, caused only by the technology process. Increasing cost of chip production $ Decreasing yield of chip production

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 35 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Development of different parameters in computer architecture in the past