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Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Architectures and Diagnosis Methods for Self Repairing.

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Präsentation zum Thema: "Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Architectures and Diagnosis Methods for Self Repairing."—  Präsentation transkript:

1 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Architectures and Diagnosis Methods for Self Repairing Logic H. T. Vierhaus BTU Cottbus Computer Engineering

2 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Outline 1. Parameters for Self Repair Functions 2. Self Repair Based on FPGAs 3. PLAs and CPLDs 4. Duplication and Switched Logic Blocks 5. Fault Diagnosis and Fault Administration 6. Test and Fault Diagnosis 7. Some Parameters in Comparison 8. Summary and Conclusions

3 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Basic Parameters for BISR Fault densities that can be managed Overhead (chip area, time, dissipated power) Types of faults that can / cannot be repaired Compatibility with standard CMOS processes Applicability to BISR in a production - test environment or in the field of application

4 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Repair Granularity and Fault Density Granularity (transistors) trans.gate FPGA block Makro- Ersatz (CPU etc.) Hardly explored (logic) Granularity (transistors) trans.gate RT- macro cores CPU Block- Ersatz (ALU etc.) Expected fault density (1 out of..) Logic / Gate Level Ersatz

5 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Repair Overhead versus Element Loss Size of replaced blocks (granularity) Repair procedure overhead Functioning elements lost k10k100k1M10M Prohibitive overhead Prohibitive fault density New Methods and Archi- techtures

6 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Block Structure of FPGAs Programmable interconnects

7 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus FPGA Experiences FPGA repair schemes that discard a whole row or column of CLBs are simple to implement but inefficient, as they lose many functional CLBs for a single fault. FPGA schemes that reserve single CLBs in the matrix for backup and do repair by single CLB replacement are much more difficult to implement because of the necessary irregular-wiring process.

8 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus FPGA with Irregular Repair Scheme CLB backupblock (reserved) functionally used CLBs rowwith faultyCLB used CLBs Programmable interconnects Backup block used for replacement

9 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus BISR by Standard FPGAs ? Configurable logic blocks (CLBs) are rather large ( transistors, estimated) FPGAs are heterogeneous by nature: - memory-like lookup tables - logic elements (selectors, decoders, flip-flops, embedded arithmetic units) - local and global programmable interconnects with additional elements for programmability - embedded CPUs. For fault densities below about 1 in , repair must go into CLBs or slices !

10 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Structure of a CLB Slice

11 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Look-up-Table

12 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Self Repair within FPGA Basic Blocks Heterogeneous repair strategies required (memory, logic) Logic blocks may use methods known from memory BISR Additional repair strategies are necesssary for logic elements The basic overhead for FPGAs versus standard logic (about 10) is enhanced. Repair strategies for logic may use some features already used in FPGAs (e. g. switched interconnects).

13 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Flip-Flop Backup Scheme

14 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus PLA- like Structures

15 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus PLA Repair Scheme Switching Unit Switching unit Specific programming of cross points !

16 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus FPGA / CPLD Repair Looks pretty easy at first glance because of regular architecture Requires lines / colums of switches for configuration at inputs and between AND / OR matrices Requires additional programmability of cross-points by double-gate transistor as in EEPROMs or Flash memory Not fully compatible with standard CMOS Limited number of (re-) configurations Floating gate (FAMOS) transistors are fault-sensitive !

17 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Double-Gate Transistors

18 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Cell Duplication

19 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Cell Duplicaton Simple scheme involving VDD off / on switch Inherent duplication of efforts VDD separation of fault cells Extra effort for output isolation of fault cells necessary. Input isolation (input gate shorts) is not easily possible. Relatively large overhead for managing repair states and redundance (re-) organisation. Fully CMOS compatible

20 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Block Organization in Random Logic

21 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Logic Cluster Architecture A number of equal-type logic gates makes a cluster The cluster contains one or more spare gates A spare gate may replace a normal device, modification is done via sets of input / output selctors / de-selectors Problems: Input gate short of a normal device is not fully isolated For n gates alternatively mapped to a single backup device, there are (n+1) control states. Switching elements are complex and not fault tolerant By themselves.

22 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Modified Cluster Architecture Can possibly isolate a specific gate, but still requires lots of administrative overhead.

23 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Reconfiguration by Permutation Schemes 2-Way Switch state 0 state 1 grounded faulty inputs / outputs

24 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Specific Features Only 4 logic states for permutation in a cluster of 8 logic blocks including 2 for backup. All single failed blocks plus some double failures can be compensated. Failed components are isolated and input / output grounded. Input gate shorts can be handled. Internal blocks may have different complexities depending on anticipated fault density. Simple switching devices, fully CMOS compatible. Fault tolerant switching devices need extra effort !

25 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Fault Tolerant Switch s s ss inout Switching elements can be made fault-tolerant by themselves, both for on- and off-type faults !... but at the cost of extra delays !

26 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Test, Diagnosis, Fault Administration For self rapair in the field of application, fault diagnosis must identify faulty elements that can be replaced. The granularity of fault diagnosis is therefore depending on the granularity of replacement (gates, RT-elements, CPUs) Conventional fault diagnosis in scan-based test is limited to the respective position in a scan chain. As scan chains are often allocated in a random manner without a strict reference to RT-level architectures, diagnosis methods used with production test are not a real solution. A system that has redundant elements and self-repair functions must restore a working status after power-off periods by: - storage and re-assembly of the previous status of repair, or by - self test, fault diagnosis and re-configuration after start-up.

27 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Test and Redundancy Administration System With BISR Capability Redundant Elements CPU Repair Status Memory Status control... makes a significant overhead beyond redundancy provision !

28 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Test and Diagnostic Resolution (1) Scan-in Scan-out G1G2G3G4G5 G7G8G9G10 G11G12G13 G6 Scan test can only identify faulty scan-out location !

29 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Test and Diagnostic Resolution (2) Scan-in Scan-out G1G2G3G4G5 G7G8G9G10 G11G12G13 G6 Scan test can only identify faulty scan-out location ! Non-resolvable fault ! Further resolution by multiple test patterns !

30 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Production Test with Diagnosis Test Fault Detection Diagnosis Scan-Path Nr., Bit-Nr. Fault simulation Layout Chip-Analysis On-line Off-line.. is not available in the field !

31 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Diagnosis by Tentative Repair

32 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Tentative Repair Switch-off of faulty elements and power separation are often done by fuses. Once a fuse is blown, it cannot be re-installed !! Reconfiguration schemes based on fuse or antifuse switching elements cannot be used in conjunction with tentative repair.

33 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Enhanced Logic Cluster Extra scan outs at extra blocks

34 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Diagnostic Test In a bundle of 8 blocks and with 2 extra outputs. By going through the 4 logic states of (re-)configuration, each block is once connected to the spare inputs and outputs. If a test pattern is applied to 4 units of the same type by going through the 4 states, the faulty unit can be identified. The false output detection can be used locally to set a status of re-configuration. With multiple units of the same type tested in parallel, time and overhead are resonable. If tests are short and reliable, an initial test process after every power-down can be performed. Keeping configurations in a memory is not necessary.

35 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Local Test and Reconfiguration

36 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Integrated Test & Repair logicR BIST&Repair logicR BIST&Repair logicR BIST&Repair logicR BIST&Repair logicR BIST&Repair logicR BIST&Repair Global Control BIST start Monitoring of repair resources exhausted conditions

37 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Comparison

38 Lehrstuhl Technische Informatik - Computer Engineering Brandenburgische Technische Universität Cottbus Summary Several types of logic (FPGAs, CPLDs) require either an inhomogeneous replacement process based on different types of redundant elements. Repair schems that need special devices (e. g. floating gate transistors) are not attractive. Schemes that provide a high level of fault isolation for short-type faults are most attractive. Architectures that also provide excellent local (self-) test coupled to locally organized self repair are possible.


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